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Job Description:
Individual will lead a team of verification engineers tasked with delivery of key components for next generation product. He/She will be responsible for task assignments, schedule and coordination of activities with multi site team. This is a “hands on” position and candidate expected to participate in active verification process. Activities will include test plan development & execution, coverage analysis, Assertion implementation, gate level simulation and support of emulation platforms. Significant effort will be placed on the integration and verification of SOC modules. In addition, individual will be part of DV team working on transition to UVM based verification process and will support the implementation of components needed for new verification environment.
Expereince:
Demonstrated leadership experience on a verification project.
Working knowledge of UVM, OVM or VMM process is considered highly desirable. Strong Verilog skills and competency with Perl scripting language needed. Candidate should also be comfortable writing code in the C programming language. Any experience working with compressed digital video formats is beneficial. Familiarity with Synopsis VCS and Verification IP will be considered pluses.
A minimum of 10 years solid DV experience needed with at least 5 years of leadership.
Comments:
Individual is expected to be self starter and be able to work with/train other team members.
