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Responsibilities:
- DFT: full scan insertion, ATPG, test compression, transition delay faults (TDF), physical test - bridging faults - preferred
- RAM BIST: memory BIST generation, built-in self repair
- Boundary Scan: AC JTAG, DC JTAG
- Logic BIST
- Serdes BIST (preferred)
Maintaining a minimum coverage metrics and support Operations with Production "bring-up". Interface with other groups within the company, including front end design engineering, physical design engineering, product engineering and production test. Interface with tool and IP vendors for day to day usage issues and for evaluation of new products.
Required Experience:
- 4+ years of DFT experience including demonstrated tape-outs in 90nm/65nm and below
- Hands on experience with all aspects of DFT in a COT back-end flow
- Proficiency with VCS, Primetime, Tetra-MAX, DFT Compiler and BSD Compiler
- Proficiency in script writing; Perl, tcl, make, Linux/Unix shell script
- Proficiency in analyzing reports from DFT and STA tools
- Proficiency in logic design and Verilog coding and analysis
- Understanding of CMOS circuit design and analysis
- Good oral and written communication skills
