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Description:
The individual in this position will be responsible for delivering blocks in hierarchical chips for tape-out in a timely, high quality, cost-effective manner. The individual must have demonstrated success in implementing complex high speed blocks in 65nm and below technologies. This position will work closely with the RTL Design, DFT design, packaging and foundry teams. Must have deep technical knowledge and proven technical expertise in taking large blocks to timing & physical design closure.
Key Responsibilities
• Implement physical design from floor-planning to tape-out in 65nm and below technologies.
• Drive multiple blocks at the same time towards P&R/STA/DRC-LVS and IR Drop closure.
• Work with different teams to resolve bottlenecks.
• Develop and enhance flows and tool methodologies to meet design TAT.
• Project planning skills with strong sense of ownership to complete projects on schedule and meet design targets.
• The responsibility also spans into the low power area focusing on low power physical design flows and methodologies like Power Gating, Voltage scaling, Frequency scaling etc.
Required Experience:
• Expert level knowledge and hands on experience in an industry standard Place & Route Suites ¨C Synopsys &/or Cadence.
• Strong Working Knowledge of Primetime and Extraction Tools.
• Expert knowledge of TCL and Perl/csh scripting.
• Working Knowledge of DRC/LVS issues and fixes.
• Experience with multiple chip tape outs and driving silicon to production.
• Familiarity with new issues in 65nm and 40 nm nodes such as DFM.
• Experience working with EDA vendors and Silicon Foundries.
• Ability to work cross-functionally within a relatively flat organization.
• Driven self-starter; clear and logical thinker; and attention to details.
• Solid work ethic and strong time management that gets things done, on time, every time.
Required Education:
BSEE or equivalent; MSEE preferred.
