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Responsibilities
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As a key member of a nascent but high visibility functional verification team responsible for the verification infrastructure, environment and testing of next generation PLX products.
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Work with Verification Architect to define the verification methodology, implement verification infrastructure and specification of all common, sharable modules and utilities.
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Responsible for detailed test plans for design modules that you will verify.
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Implement highly complex verification environments, including stimulus and checking modules, for design products. As part of this, you will create, run, debug and track tests against design products and then you will specify, implement and track test and code coverage on design products. Ultimately, you will be the owner to ensure the proposed design implementation meets standards and design requirements.
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Workwithtoolvendorstotrackandresolveproblems.
Required Experience
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Familiar with OOP and have coding and debugging experience in System Verilog/Vera/NTB. Designed BFM or other verification components in production systems.
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Familiar with any of RVM, OVM, VMM, UVM a huge plus.
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Have already gone through multiple tape outs of ASIC's working in the functional verification process before and after tape outs.
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Knowledge of at least one language of each of the following: a shell script (sh/csh/tcsh/bash), a scripting language (Perl/Tcl/Python/JavaScript) and a programming language (C/C++/Java) above and beyond Verilog and System Verilog.
Preferred Skills & Experience:
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In-depth knowledge and experience based on production quality developments with SystemVerilog.
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Enthusiastic about design patterns, object oriented versus aspect oriented design, singleton class versus derived ones.
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Familiar with PCIe/Ethernet/USB
Required Education:
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BSEE/MSEE or equivalent.
