|
|
Primary Responsibilities:
In the position, the employee will be responsible for complete physical design of large,
complex blocks for Achronix's FPGA products in Intel's 22nm process.
Working on one or more blocks, which will include the following activities:
• Complete physical synthesis
• CTS
• Routing & DFM
• Physical verification
Skills:
• Expertise in Physical activities: Floor-planning, clock tree synthesis, P&R
extraction, IR drop analysis, STA, physical verification and signal integrity.
• Hands on experience in ICC/Talus/Cadence tools. Experience in ICC would be a plus
• A good understanding of layout DRC rules and concepts, device identification concepts
• Prior experience in Process Technology node 40nm and lower.
• Experience supporting layout teams and displaying solid programming knowledge in Perl, TCL, and/or Shell Scripting
• A Highly driven individual with the ability to take ownership of assigned tasks in an exciting, but challenging start-up environment
• Good communication skills
Experience/ Education:
4-9 years of experience in physical design
